This invention relates generally to first-in, first-out (FIFO) memory systems and more particularly, it relates to an interleaved sensing system used especially with FIFO and burst-mode memories for decreasing the read access time and thus its overall speed of operation.
As is generally known, a FIFO is essentially a data buffer in which data is shifted out in the same chronological order as it was shifted in with the shifting in and shifting out operations generally being able to function simultaneously and at the same or different speeds. Memory system designers have developed heretofore memory systems having FIFO memory units wherein data that is entered into the memory system will be sequentially passed therethrough. Typically, these prior art FIFO systems are implemented using a random-access-memory (RAM) and switching circuits controlled by a column decoder located near the ends of the bit lines. During a read cycle, one of the switching circuits is made conductive so as to precharge the data lines. Therefore, a great deal of time is required for setting up the data lines to a predetermined potential when the stray capacitance is large. Thus, this precharge time of the data lines restricts the speed of these prior art FIFO systems.
Referring to the set of waveforms in FIGS. 1(a)-1(e), there is shown a general read cycle timing of the prior art FIFO systems. As can be seen, the steps of (1) precharging of the data lines to be used, (2) activating of the column select transistors for coupling the bit lines with the data lines, and (3) transferring of the data to the output are all performed in one read cycle between the times t1 to t2. Consequently, a relatively large read cycle time is required.
It would therefore be desirable to provide an interleaved sensing system for use with FIFO and burst-mode memories for decreasing its read access time. This is achieved in the present invention by providing two paths from the bit lines in the FIFO RAM array so as to permit the read operation to take place over two cycles rather than a single cycle of the prior art. This can be best understood by reference to the set of waveforms in FIGS. 2(a)-2(f), which illustrates the general read cycle timing of the present invention. The data that is to appear on the output during the read cycle (between the times tA to tB) is begun to be read from the FIFO RAM array one cycle earlier. At the time t1, the data lines to be used are precharged. At the time t2, the column select signal is used to activate select transistors located between the bit lines and the data lines. As a result, the data on the bit lines will be transferred to the data lines during the next cycle. At the time t3, which is one full cycle later, a multiplexer is enabled by the read signal of FIG. 2(d) so as to select the appropriate sense amplifier. At the time t4, the output buffer is enabled so as to transfer the data from the sense amplifier to the output at the time t5.